1. Field of the Invention
This invention relates to dynamic semiconductor memories, and more particularly to a dynamic semiconductor memory having an enlarged operating margin for information reading and a reduced soft error rate.
2. Description of the Background Art
FIG. 8 is a block diagram showing an example of commonly known dynamic semiconductor memories (which are referred to hereinafter as DRAMs or dynamic random access memories).
Referring to the drawing, this DRAM comprises a memory cell array 508 including a plurality of memory cells arranged in a matrix form for storing data signals, an address buffer 504 for receiving address signals to select the memory cells, a row decoder 505 and a column decoder 506 for decoding the address signals, and a sense amplifier 603 connected to the memory cell array 508 for amplifying and reading out the signals stored in the memory cells. An input buffer 509 for inputting the data signals and an output buffer 600 for outputting the data signals are connected to the memory cell array 508 through an I/O gate 507.
The address buffer 504 is connected to receive external address signals ext. A0-A9.
FIG. 9 is a view showing the specific construction of a portion of the memory cell array 508 and sense amplifier 603 shown in FIG. 8.
In the drawing, word lines WL1 and WL2 and dummy word lines DWLo and DWLe are arranged to extend in a direction intersecting bit lines BL and BL. A memory cell selecting transistor QM1 and a capacitor MC1 constituting a memory cell are connected in series to an intersection of word line WL1 and bit line BL. A similar memory cell is connected also to an intersection of word line WL2 and bit line BL. Further, a dummy cell selecting transistor QD and a dummy cell capacitor DC0 constituting a dummy cell are connected in series to an intersection of dummy word line DWLo and bit line BL. Similarly, a dummy cell is connected to an intersection of dummy word line DWLe and bit line BL.
One end of each of the bit lines BL and BL is coupled to a precharge potential V.sub.PRC through a precharge transistor QP or QP'. The precharge potential V.sub.PRC is maintained at a potential of Vcc/2. Further, the bit lines BL and BL are interconnected through a transistor QE. A precharge signal .phi..sub.PRC is applied to the respective gates of transistors QP, and QP' and QE. A sense amplifier SA is connected to bit lines BL and BL for detecting and amplifying a potential difference occurring between the bit lines. The sense amplifier SA is applied with ground potential through a transistor Q1 and source potential Vcc through a transistor Q2. A sense amplifier activating signal .phi..sub.S is applied to the gate of transistor Q1. A sense amplifier activating signal .phi..sub.S is applied to the gate of transistor Q2.
The other ends of bit lines BL and BL are connected to input and output lines I/O and I/O through transistors QT and QT' constituting the I/O gate 507, respectively. A decode signal is applied by the column decoder 506 to the gates of transistors QT and QT'.
An operation of the semiconductor memory shown in FIGS. 8 and 9 will be described next with reference to the timing chart of FIG. 10.
When external signal ex.RAS falls, the potential of word lines WL is raised to "H" level. Simultaneously the potential of one of the dummy word lines DWLo and DWLe falls.
On the other hand, the output of precharge signal .phi..sub.PRC becomes "L" level before the potential level of the word lines rises, thereby placing the bit lines in the floating state. When word line WL1 is selected, for example, the potential of word line WL rises to "H", and at the same time dummy word line DWLo is selected with its potential falling to "L" level. Consequently, the memory cell selecting transistor QM1 becomes conductive to connect memory cell MC1 to bit line BL. When, for example, an "H" level potential is stored in memory cell MC1 connected to bit line BL, the potential of bit line BL rises by a value determined by a ratio between its stray capacitance C.sub.BL and capacity C.sub.S of memory cell MC. On the other hand, the potential of bit line BL remains at Vcc/2 and serves as a reference potential for the potential of bit line BL. Subsequently, sense amplifier activating signal .phi..sub.S becomes "H" level, and signal .phi..sub.S becomes "L" level, whereby the sense amplifier SA is activated through transistors Q1 and Q2. As a result, the potential of bit line BL becomes Vcc, while the potential of bit line BL becomes ground potential, to complete a sense operation. In the series of operating steps as described above, the potential of bit line BL rises with the rise of the potential of word line WL1, which is due to a capacity coupling through stray capacitance CP present between a connection of memory cell selecting transistor QM1 with bit line BL and word line WL1 as shown in FIG. 11, and which affects the operating margin for signal reading. Particularly, when an "L" level potential is stored in memory cell MC1, the potential of bit line BL rises due to the capacity coupling. As a result, what should be lower than the potential of bit line BL becomes higher, thereby causing an error of reading "L" level information as "H" level information. Dummy cell DC is provided in order to cancel this potential variation of bit line BL. By causing the potential of dummy word line DWLo to fall with selection of word line WL1, bit line BL is applied with what is opposite and corresponds in degree to the potential variation occurring on bit line BL when word line WL1 rises. That is, the influence of the potential variation upon the reading operation is eliminated by applying an opposite and an equivalent potential variation to bit line BL.
FIG. 12 is a view schematically showing the construction of a memory cell array in a known DRAM employing the folded bit line system.
In the drawing, a plurality of bit line pairs BL (BL.sub.A -BL.sub.E) and BL (BL.sub.A -BL.sub.E) are arranged to intersect a plurality of word lines WL (WL1-WL4). Memory cells MC are arranged at and connected to intersections of bit lines BL or BL and word lines WL in opposed relationship to folded bit lines. Bit lines BL.sub.A and BL.sub.A, BLB and BL.sub.B, . . . BL.sub.E and BL.sub.E forming pairs are connected to sense amplifiers SA.sub.A, SA.sub.B, . . . SA.sub.E, respectively.
The manner in which information is read from memory cell MC1 will be described now. As described with reference to FIGS. 9 and 10, the potential of word line WL1 rises first, and data are read from the memory cells connected to word line WL1. Looking at the entire memory cell array, data are output to bit lines BL.sub.A -BL.sub.E. Bit lines BL.sub.A -BL.sub.E forming the pairs with the bit lines for which the data are read, act as reference bit lines and are maintained at a reference potential. Thereafter sense amplifiers SA.sub.A -SA.sub.E are activated to amplify the data read out.
Potentials of the bit lines forming a pair in data reading will be calculated. A potential difference between bit lines BL.sub.B and BL.sub.B in FIG. 12 is determined as one of example here. FIG. 13 shows an equivalent circuit for this case. In FIG. 13, reference C.sub.1 denotes a capacitance occurring between each bit line and ground potential through a substrate, C.sub.2 a capacitance between adjacent bit lines, C.sub.M a capacity of each memory cell, and C.sub.D a capacity of each dummy cell. It is assumed that bit lines BL.sub.B and BL.sub.B have potentials V.sub.BLB and V.sub.BLB, respectively, and that the precharge level of the bit lines is Veq. The potentials of other bit lines BL.sub.A, BL.sub.A, BL.sub.C and BL.sub.C are assumed to be V.sub.BLA, V.sub.BLA, V.sub.BLC and V.sub.BLC, respectively.
The following equation is formed for the charges of bit line BL.sub.B before and after the data reading: ##EQU1##
The plus sign "+" in the parenthesis of the coefficient of Vcc in the left side of the equation signifies that the memory cell stores "H" level information (V.sub.cc writing), while the minus ("-") sign signifies that the memory cell stores "L" level information ((0 V) writing). The left side shows the charges stored in capacitance C.sub.1 and capacity C.sub.S of the memory cell before the data reading. The right side shows the charges stored in capacitance C.sub.1, capacitance C.sub.2 between adjacent bit lines and memory cell capacity C.sub.M after the data reading.
Similarly, the following equation is formed for the potential of bit line BL.sub.B : ##EQU2##
The left side of equation (2) shows the charges stored in capacitance C.sub.1 and capacit C.sub.D of the dummy cell before the data reading. The right side shows the charges stored in capacitance C.sub.1, capacitance C.sub.2 between adjacent bit lines and dummy cell capacit C.sub.D after the data reading. Capacity of the dummy cell is set equal to capacit C.sub.M of the memory cell to serve the intended purpose. A further calculation is made as follows, with C.sub.S representing the capacity of the dummy cell and memory cell.
When the data are output to bit line BL.sub.B, the potential of bit line BL.sub.B is at the reference potential. Potential difference .DELTA.V between bit lines BL.sub.B and BL.sub.B are derived from equations (1) and (2) as follows: EQU .DELTA.V=.vertline.V.sub.BLB -V.sub.BLB .vertline.=C.sub.S V.sub.cc /2(C.sub.1 +4C.sub.2 +C.sub.S) (3)
Thus, when capacitance C.sub.2 between the bit lines increases with the array having an increasingly fine structure or for other reasons, potential difference .DELTA.V decreases since C.sub.1 and C.sub.S are constant, which tends to reduce the reading margin and deteriorate the soft error. Further, at times of sense amplification, capacitance C.sub.2 acts as a source of noise for the amplification of data, thereby likewise deteriorating the operating margin.